In CMOS technology, performance degradation of power is one of the foremost questions at daily vitality. In this circuit, power dissipation is increasing exponentially constantly with technology scaling down. The analog to digital converters (ADCs) are the vital branch of signal processing and communication system. In digital region power consumption and low voltage develop into wide component is difficult for conniving high speed devices and converters. In this paper we have presented a complete investigation of 3 bits flash ADC circuit by using low leakage stacked power gating technique and diode based stacked power gating technique.
These techniques are reduces the leakage current and average power in standby mode effectively. In this circuit, with the stacked power gating technique, leakage current and average power is reduced is by up to 77% and 99% respectively. Diode based stacked power gating technique can be identified as the most effective technique. With this technique, leakage current is 1.241 nA at 0.7 V and average power is 3.49 nW at 0.7 V. To evaluate of power gating techniques, the simulation has been performed using cadence virtuoso tool at assorted power supply by 45nm technology.