NS3 in MS

In this work, we are making 802.11 WLAN Channel specific energy efficient ALU using the HSUL_12 (High Speed Unterminated Logic) IO standard. This ALU design is implemented on FPGA. In this experiment, Xilinx 14.6 is used as simulator, Verilog is used as verification language and XPower is the power consumption estimator. Capacitance scaling technique is used for reduction in IOs power. We scale down the output load capacitance value from 5555pF to 555pF, 55pF, and 5pF.

There is a 94.83% reduction in IO Power as we scale down the capacitance value. There is 92.19% reduction in Leakage Power because of capacitance scaling. The reduction in total power is 94.54% on account of capacitance scaling. In order to test the compatibility of our ALU design with WLAN, we are operating our ALU with specified frequency of WLAN Channel e.g. 802.11ah (0.9 GHz), 802.11b/g/n (2.4 GHz), 802.11y (3.6 GHz), 802.11y (4.9 GHz), 802.11a/h/j/n/ac (5 GHz), 802.11p (5.9 GHz), and 802.11ad (60 GHz).